Datasheet

V850ES/JG3 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
R01UH0015EJ0300 Rev.3.00 Page 450 of 870
Sep 30, 2010
15.2 Features
Transfer rate: 300 bps to 625 kbps (using internal system clock of 32 MHz and dedicated baud rate generator)
Full-duplex communication: Internal UARTAn receive data register (UAnRX)
Internal UARTAn transmit data register (UAnTX)
2-pin configuration: TXDAn: Transmit data output pin
RXDAn: Receive data input pin
Reception error output function
• Parity error
• Framing error
• Overrun error
Interrupt sources: 2
• Reception complete interrupt (INTUAnR): This interrupt occurs upon transfer of receive data from the receive
shift register to receive data register after serial transfer completion,
in the reception enabled status.
• Transmission enable interrupt (INTUAnT): This interrupt occurs upon transfer of transmit data from the
transmit data register to the transmit shift register in the
transmission enabled status.
Character length: 7, 8 bits
Parity function: Odd, even, 0, none
Transmission stop bit: 1, 2 bits
On-chip dedicated baud rate generator
MSB-/LSB-first transfer selectable
Transmit/receive data inverted input/output possible
SBF (Sync Break Field) transmission/reception in the LIN (Local Interconnect Network) communication format
possible
• 13 to 20 bits selectable for SBF transmission
• Recognition of 11 bits or more possible for SBF reception
• SBF reception flag provided
Remark n = 0 to 2