Datasheet

V850ES/JG3 CHAPTER 14 D/A CONVERTER
R01UH0015EJ0300 Rev.3.00 Page 446 of 870
Sep 30, 2010
14.4.3 Cautions
Observe the following cautions when using the D/A converter of the V850ES/JG3.
(1) Do not change the set value of the DA0CSn register while the trigger signal is being issued in the real-time output
mode.
(2) Before changing the operation mode, be sure to clear the DA0M.DA0CEn bit to 0.
(3) When using one of the P10/AN00 and P11/AN01 pins as an I/O port and the other as a D/A output pin, do so in an
application where the port I/O level does not change during D/A output.
(4) Make sure that AV
REF0 = VDD = AVREF1 = 3.0 to 3.6 V. If this range is exceeded, the operation is not guaranteed.
(5) Apply power to AV
REF1 at the same timing as AVREF0.
(6) No current can be output from the ANOn pin (n = 0, 1) because the output impedance of the D/A converter is high.
When connecting a resistor of 2 MΩ or less, insert a JFET input operational amplifier between the resistor and the
ANOn pin.
Figure 14-2. External Pin Connection Example
AV REF1
V DD
Output
10 F
0.1 F
10 F
0.1 F
AV
REF0
ANOn
AV
SS
−
+
JFET input
operational amplifier
μ
μ
μ
μ
(7) Because the D/A converter stops operation in the STOP mode, the ANO0 and ANO1 pins go into a high-impedance
state, and the power consumption can be reduced.
In the IDLE1, IDLE2, or subclock operation mode, however, the operation continues. To lower the power
consumption, therefore, clear the DA0M.DA0CEn bit to 0.