Datasheet

V850ES/JG3 CHAPTER 3 CPU FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 30 of 870
Sep 30, 2010
(2) NMI status saving registers (FEPC and FEPSW)
FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs.
If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status
word (PSW) are saved to FEPSW.
The address of the instruction next to the one of the instruction under execution, except some instructions, is saved
to FEPC when an NMI occurs.
The current contents of the PSW are saved to FEPSW.
Because only one set of NMI status saving registers is available, the contents of these registers must be saved by
program when multiple interrupts are enabled.
Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion (these bits are always
fixed to 0).
The value of FEPC is restored to the PC and the value of FEPSW to the PSW by the RETI instruction.
31 0
FEPC
(Saved PC contents) 00
Default value
0xxxxxxxH
(x: Undefined)
26 25
0 0 0 0
31 0
FEPSW
(Saved PSW
contents)
00
Default value
000000xxH
(x: Undefined)
87
0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0
(3) Interrupt source register (ECR)
The interrupt source register (ECR) holds the source of an exception or interrupt if an exception or interrupt occurs.
This register holds the exception code of each interrupt source. Because this register is a read-only register, data
cannot be written to this register using the LDSR instruction.
31 0
ECR
FECC EICC
Default value
00000000H
16 15
Bit position Bit name Meaning
31 to 16 FECC Exception code of non-maskable interrupt (NMI)
15 to 0 EICC Exception code of exception or maskable interrupt