Datasheet

V850ES/JG3 CHAPTER 3 CPU FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 29 of 870
Sep 30, 2010
(1) Interrupt status saving registers (EIPC and EIPSW)
EIPC and EIPSW are used to save the status when an interrupt occurs.
If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC,
and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI
status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).
The address of the instruction next to the instruction under execution, except some instructions (see 19.8 Periods
in Which Interrupts Are Not Acknowledged by CPU), is saved to EIPC when a software exception or a maskable
interrupt occurs.
The current contents of the PSW are saved to EIPSW.
Because only one set of interrupt status saving registers is available, the contents of these registers must be saved
by program when multiple interrupts are enabled.
Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved for future function expansion (these bits are always
fixed to 0).
The value of EIPC is restored to the PC and the value of EIPSW to the PSW by the RETI instruction.
31 0
EIPC
(Saved PC contents) 00
Default value
0xxxxxxxH
(x: Undefined)
26 25
0 0 0 0
31 0
EIPSW
(Saved PSW
contents)
00
Default value
000000xxH
(x: Undefined)
87
0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0