Datasheet

V850ES/JG3 CHAPTER 13 A/D CONVERTER
R01UH0015EJ0300 Rev.3.00 Page 429 of 870
Sep 30, 2010
13.5.5 Power-fail compare mode
The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and ADA0PFT
registers.
• When the ADA0PFM.ADA0PFE bit = 0, the INTAD signal is generated each time conversion is completed (normal
use of the A/D converter).
• When the ADA0PFE bit = 1 and when the ADA0PFM.ADA0PFC bit = 0, the value of the ADA0CRnH register is
compared with the value of the ADA0PFT register when conversion is completed, and the INTAD signal is generated
only if ADA0CRnH ≥ ADA0PFT.
• When the ADA0PFE bit = 1 and when the ADA0PFC bit = 1, the value of the ADA0CRnH register is compared with
the value of the ADA0PFT register when conversion is completed, and the INTAD signal is generated only if
ADA0CRnH < ADA0PFT.
Remark n = 0 to 11
In the power-fail compare mode, four modes are available as modes in which to set the ANI0 to ANI11 pins: continuous
select mode, continuous scan mode, one-shot select mode, and one-shot scan mode.