Datasheet

V850ES/JG3 CHAPTER 3 CPU FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 28 of 870
Sep 30, 2010
3.2.2 System register set
The system registers control the status of the CPU and hold interrupt information.
These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the
system register numbers listed below.
Table 3-2. System Register Numbers
Operand Specification System
Register
Number
System Register Name
LDSR Instruction STSR Instruction
0 Interrupt status saving register (EIPC)
Note 1
√ √
1 Interrupt status saving register (EIPSW)
Note 1
√ √
2 NMI status saving register (FEPC)
Note 1
√ √
3 NMI status saving register (FEPSW)
Note 1
√ √
4 Interrupt source register (ECR)
× √
5 Program status word (PSW)
√ √
6 to 15 Reserved for future function expansion (operation is not guaranteed if these
registers are accessed)
× ×
16 CALLT execution status saving register (CTPC)
√ √
17 CALLT execution status saving register (CTPSW)
√ √
18 Exception/debug trap status saving register (DBPC) √
Note 2
√
Note 2
19 Exception/debug trap status saving register (DBPSW) √
Note 2
√
Note 2
20 CALLT base pointer (CTBP)
√ √
21 to 31 Reserved for future function expansion (operation is not guaranteed if these
registers are accessed)
× ×
Notes 1. Because only one set of these registers is available, the contents of these registers must be saved by
program if multiple interrupts are enabled.
2. These registers can be accessed only during the interval between the execution of the DBTRAP instruction
or illegal opcode and the DBRET instruction.
Caution Even if EIPC or FEPC, or bit 0 of CTPC is set to 1 by the LDSR instruction, bit 0 is ignored when
execution is returned to the main routine by the RETI instruction after interrupt servicing (this is
because bit 0 of the PC is fixed to 0). Set an even value to EIPC, FEPC, and CTPC (bit 0 = 0).
Remark √: Can be accessed
×: Access prohibited