Datasheet

V850ES/JG3 CHAPTER 13 A/D CONVERTER
R01UH0015EJ0300 Rev.3.00 Page 415 of 870
Sep 30, 2010
(3) A/D converter mode register 2 (ADA0M2)
The ADA0M2 register specifies the hardware trigger mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0ADA0M2 0 0 0 00 ADA0TMD1 ADA0TMD0
ADA0TMD1
0
0
1
1
ADA0TMD0
0
1
0
1
Specification of hardware trigger mode
External trigger mode (when ADTRG pin valid edge detected)
Timer trigger mode 0
(when INTTP2CC0 interrupt request generated)
Timer trigger mode 1
(when INTTP2CC1 interrupt request generated)
Setting prohibited
After reset: 00H R/W Address: FFFFF203H
65432107
Cautions 1. When writing data to the ADA0M2 register in the following modes, stop the A/D
conversion by clearing the AD0M0.ADA0CE bit to 0. After the data is written to the
register, enable the A/D conversion again by setting the ADA0CE bit to 1.
• Normal conversion mode
• One-shot select mode/one-shot scan mode in high-speed conversion mode
2. Be sure to clear bits 7 to 2 to “0”.