Datasheet
V850ES/JG3 CHAPTER 13 A/D CONVERTER
R01UH0015EJ0300 Rev.3.00 Page 414 of 870
Sep 30, 2010
Table 13-3. Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1)
A/D Conversion Time
ADA0FR3 to
ADA0FR0 Bits
Conversion Time
(+ Stabilization Time)
f
XX = 32 MHz fXX = 20 MHz fXX = 16 MHz fXX = 4 MHz
Trigger
Response
Time
0000 26/fXX (+ 13/fXX) Setting prohibited Setting prohibited
Setting prohibited
6.5
μ
s
(+ 3.25
μ
s)
3/f
XX
0010 52/fXX (+ 26/fXX)
Setting prohibited 2.6
μ
s
(+ 1.3
μ
s)
3.25
μ
s
(+ 1.625
μ
s)
Setting prohibited 3/f
XX
0010 78/fXX (+ 39/fXX)
Setting prohibited 3.9
μ
s
(+ 1.95
μ
s)
4.875
μ
s
(+ 2.4375
μ
s)
Setting prohibited 3/f
XX
0011 104/fXX (+ 50/fXX)
3.25
μ
s
(+ 1.5625
μ
s)
5.2
μ
s
(+ 2.5
μ
s)
6.5
μ
s
(+ 3.125
μ
s)
Setting prohibited 3/f
XX
0100 130/fXX (+ 50/fXX)
4.0625
μ
s
(+ 1.5625
μ
s)
6.5
μ
s
(+ 2.5
μ
s)
8.125
μ
s
(+ 3.125
μ
s)
Setting prohibited 3/f
XX
0101 156/fXX (+ 50/fXX)
4.875
μ
s
(+ 1.5625
μ
s)
7.8
μ
s
(+ 2.5
μ
s)
9.75
μ
s
(+ 3.125
μ
s)
Setting prohibited 3/f
XX
0110 182/fXX (+ 50/fXX)
5.6875
μ
s
(+ 1.5625
μ
s)
9.1
μ
s
(+ 2.5
μ
s)
Setting prohibited Setting prohibited 3/f
XX
0111 208/fXX (+ 50/fXX)
6.5
μ
s
(+ 1.5625
μ
s)
10.4
μ
s
(+ 2.5
μ
s)
Setting prohibited Setting prohibited 3/f
XX
1000 234/fXX (+ 50/fXX)
7.3125
μ
s
(+ 1.5625
μ
s)
Setting prohibited
Setting prohibited Setting prohibited 3/f
XX
1001 260/fXX (+ 50/fXX)
8.125
μ
s
(+ 1.5625
μ
s)
Setting prohibited
Setting prohibited Setting prohibited 3/f
XX
1010 286/fXX (+ 50/fXX)
8.9375
μ
s
(+ 1.5625
μ
s)
Setting prohibited
Setting prohibited Setting prohibited 3/f
XX
1011 312/fXX (+ 50/fXX)
9.75
μ
s
(+ 1.5625
μ
s)
Setting prohibited
Setting prohibited Setting prohibited 3/f
XX
Other than above Setting prohibited
Remark Conversion time: Actual A/D conversion time (2.6 to 10.4
μ
s)
Stabilization time: A/D converter setup time (1
μ
s or longer)
Trigger response time: If a software trigger, external trigger, or timer trigger is generated after the stabilization
time, it is inserted before the conversion time.
In the high-speed conversion mode, the conversion is started after the stabilization time elapsed from the
ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.6 to 10.4
μ
s). The A/D conversion end interrupt request signal (INTAD) is generated immediately after the conversion
ends.
In continuous conversion mode, the stabilization time is inserted only before the first conversion, and not
inserted after the second conversion (the A/D converter remains running).
Cautions 1. Set as 2.6
μ
s ≤ conversion time ≤ 10.4
μ
s.
2. In the high-speed conversion mode, rewriting of the ADA0M0, ADA0M2, ADA0S, ADA0PFM,
and ADA0PFT registers and trigger input are prohibited during the stabilization time.