Datasheet
V850ES/JG3 CHAPTER 13 A/D CONVERTER
R01UH0015EJ0300 Rev.3.00 Page 413 of 870
Sep 30, 2010
Table 13-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0)
A/D Conversion Time
ADA0FR3 to
ADA0FR0
Bits
Stabilization Time + Conversion
Time + Wait Time
f
XX = 32 MHz fXX = 20 MHz fXX = 16 MHz fXX = 4 MHz
Trigger Response
Time
0000 66/fXX (13/fXX + 26/fXX + 27/fXX)
Setting prohibited Setting prohibited Setting prohibited
16.50
μ
s 3/fXX
0001 131/fXX (26/fXX + 52/fXX + 53/fXX)
Setting prohibited
6.55
μ
s 8.19
μ
s
Setting prohibited
3/fXX
0010 196/fXX (39/fXX + 78/fXX + 79/fXX)
Setting prohibited
9.80
μ
s 12.25
μ
s
Setting prohibited
3/fXX
0011 259/fXX (50/fXX + 104/fXX + 105/fXX) 8.09
μ
s 12.95
μ
s 16.19
μ
s
Setting prohibited
3/fXX
0100 311/fXX (50/fXX + 130/fXX + 131/fXX) 9.72
μ
s 15.55
μ
s 19.44
μ
s
Setting prohibited
3/fXX
0101 363/fXX (50/fXX + 156/fXX + 157/fXX) 11.34
μ
s 18.15
μ
s 22.69
μ
s
Setting prohibited
3/fXX
0110 415/fXX (50/fXX + 182/fXX + 183/fXX) 12.97
μ
s 20.75
μ
s
Setting prohibited Setting prohibited
3/fXX
0111 467/fXX (50/fXX + 208/fXX + 209/fXX) 14.59
μ
s 23.35
μ
s
Setting prohibited Setting prohibited
3/fXX
1000 519/fXX (50/fXX + 234/fXX + 235/fXX) 16.22
μ
s
Setting prohibited Setting prohibited Setting prohibited
3/fXX
1001 571/fXX (50/fXX + 260/fXX + 261/fXX) 17.84
μ
s
Setting prohibited Setting prohibited Setting prohibited
3/fXX
1010 623/fXX (50/fXX + 286/fXX + 287/fXX) 19.47
μ
s
Setting prohibited Setting prohibited Setting prohibited
3/fXX
1011 675/fXX (50/fXX + 312/fXX + 313/fXX) 21.09
μ
s
Setting prohibited Setting prohibited Setting prohibited
3/fXX
Others Setting prohibited
Remark Stabilization time: A/D converter setup time (1
μ
s or longer)
Conversion time: Actual A/D conversion time (2.6 to 10.4
μ
s)
Wait time: Wait time inserted before the next conversion
Trigger response time: If a software trigger, external trigger, or timer trigger is generated after the stabilization
time, it is inserted before the conversion time.
In the normal conversion mode, the conversion is started after the stabilization time elapsed from the
ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.6 to 10.4
μ
s). Operation is stopped after the conversion ends and the A/D conversion end interrupt request signal
(INTAD) is generated after the wait time is elapsed.
Because the conversion operation is stopped during the wait time, operation current can be reduced.
Cautions 1. Set as 2.6
μ
s ≤ conversion time ≤ 10.4
μ
s.
2. During A/D conversion, if the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT
registers are written or trigger is input, reconversion is carried out. However, if the
stabilization time end timing conflicts with the writing to these registers, or if the
stabilization time end timing conflicts with the trigger input, the stabilization time of 64
clocks is reinserted.
If a conflict occurs again with the reinserted stabilization time end timing, the stabilization
time is reinserted. Therefore do not set the trigger input interval and control register write
interval to 64 clocks or below.