Datasheet

V850ES/JG3 CHAPTER 13 A/D CONVERTER
R01UH0015EJ0300 Rev.3.00 Page 408 of 870
Sep 30, 2010
(1) Successive approximation register (SAR)
The SAR register compares the voltage value of the analog input signal with the output voltage (compare voltage)
value of the compare voltage generation DAC, and holds the comparison result starting from the most significant bit
(MSB).
When the comparison result has been held down to the least significant bit (LSB) (i.e., when A/D conversion is
complete), the contents of the SAR register are transferred to the ADA0CRn register.
Remark n = 0 to 11
(2) A/D conversion result register n (ADA0CRn), A/D conversion result register nH (ADA0CRnH)
The ADA0CRn register is a 16-bit register that stores the A/D conversion result. ADA0ARn consist of 12 registers
and the A/D conversion result is stored in the 10 higher bits of the AD0CRn register corresponding to analog input.
(The lower 6 bits are fixed to 0.)
(3) A/D converter mode register 0 (ADA0M0)
This register specifies the operation mode and controls the conversion operation by the A/D converter.
(4) A/D converter mode register 1 (ADA0M1)
This register sets the conversion time of the analog input signal to be converted.
(5) A/D converter mode register 2 (ADA0M2)
This register sets the hardware trigger mode.
(6) A/D converter channel specification register (ADA0S)
This register sets the input port that inputs the analog voltage to be converted.
(7) Power-fail compare mode register (ADA0PFM)
This register sets the power-fail monitor mode.
(8) Power-fail compare threshold value register (ADA0PFT)
The ADA0PFT register sets a threshold value that is compared with the value of A/D conversion result register nH
(ADA0CRnH). The 8-bit data set to the ADA0PFT register is compared with the higher 8 bits of the A/D conversion
result register (ADA0CRnH).
(9) Controller
The controller compares the result of the A/D conversion (the value of the ADA0CRnH register) with the value of the
ADA0PFT register when A/D conversion is completed or when the power-fail detection function is used, and
generates the INTAD signal only when a specified comparison condition is satisfied.
(10) Sample & hold circuit
The sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the
sampled data to the voltage comparator. This circuit also holds the sampled analog input signal voltage during
A/D conversion.
(11) Voltage comparator
The voltage comparator compares a voltage value that has been sampled and held with the output voltage value
of the compare voltage generation DAC.