Datasheet

V850ES/JG3 CHAPTER 13 A/D CONVERTER
R01UH0015EJ0300 Rev.3.00 Page 407 of 870
Sep 30, 2010
13.3 Configuration
The block diagram of the A/D converter is shown below.
Figure 13-1. Block Diagram of A/D Converter
ANI0
:
:
ANI1
ANI2
ANI9
ANI10
ANI11
ADA0M2
ADA0M1ADA0M0 ADA0S ADA0PFT
Controller
Voltage
comparator
ADA0PFM
ADA0CR0
ADA0CR1
:
:
ADA0CR2
ADA0CR10
ADA0CR11
Internal bus
AV
REF0
ADA0CE bit
AV
SS
INTAD
Edge
detection
ADTRG
Controller
Sample & hold circuit
ADA0ETS0 bit
INTTP2CC0
INTTP2CC1
ADA0ETS1 bit
ADA0CE bit
ADA0TMD1 bit
ADA0TMD0 bit
Selector
Selector
ADA0PFE bit
ADA0PFC bit
SAR
Voltage comparator
&
Compare voltage
generation DAC
The A/D converter includes the following hardware.
Table 13-1. Configuration of A/D Converter
Item Configuration
Analog inputs 12 channels (ANI0 to ANI11 pins)
Registers
Successive approximation register (SAR)
A/D conversion result registers 0 to 11 (ADA0CR0 to ADA0CR11)
A/D conversion result registers 0H to 11H (ADCR0H to ADCR11H): Only higher 8 bits
can be read
Control registers
A/D converter mode registers 0 to 2 (ADA0M0 to ADA0M2)
A/D converter channel specification register 0 (ADA0S)
Power fail compare mode register (ADA0PFM)
Power fail compare threshold value register (ADA0PFT)