Datasheet

V850ES/JG3 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2
R01UH0015EJ0300 Rev.3.00 Page 398 of 870
Sep 30, 2010
11.4 Operation
Watchdog timer 2 automatically starts in the reset mode following reset release.
The WDTM2 register can be written to only once following reset using byte access. To use watchdog timer 2, write the
operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction. After this,
the operation of watchdog timer 2 cannot be stopped.
The WDCS24 to WDCS20 bits of the WDTM2 register are used to select the watchdog timer 2 loop detection time
interval.
Writing ACH to the WDTE register clears the counter of watchdog timer 2 and starts the count operation again. After
the count operation has started, write ACH to WDTE within the loop detection time interval.
If the time interval expires without ACH being written to the WDTE register, a reset signal (WDT2RES) or a non-
maskable interrupt request signal (INTWDT2) is generated, depending on the set values of the WDM21 and
WDTM2.WDM20 bits.
When the WDTM2.WDM21 bit is set to 1 (reset mode), if a WDT overflow occurs during oscillation stabilization after a
reset or standby is released, no internal reset will occur and the CPU clock will switch to the internal oscillation clock.
To not use watchdog timer 2, write 00H to the WDTM2 register.
For the non-maskable interrupt servicing while the non-maskable interrupt request mode is set, see 19.2.2 (2) From
INTWDT2 signal.