Datasheet

V850ES/JG3 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2
R01UH0015EJ0300 Rev.3.00 Page 395 of 870
Sep 30, 2010
11.2 Configuration
The following shows the block diagram of watchdog timer 2.
Figure 11-1. Block Diagram of Watchdog Timer 2
f XX /2
9
Clock
input
controller
Output
controller
WDT2RES
(internal reset signal)
WDCS22
Internal bus
INTWDT2
WDCS21 WDCS20
f XT
WDCS23WDCS24
0
WDM21 WDM20
Selector
16-bit
counter
f XX /2
18
to f XX /2
25
,
f
XT /2
9
to f XT /2
16
,
f
R /2
12
to f R /2
19
Watchdog timer enable
register (WDTE)
Watchdog timer mode
register 2 (WDTM2)
3
3
2
Clear
f R /2
3
Remark f
XX: Main clock frequency
f
XT: Subclock frequency
f
R: Internal oscillation clock frequency
INTWDT2: Non-maskable interrupt request signal from watchdog timer 2
WDTRES2: Watchdog timer 2 reset signal
Watchdog timer 2 includes the following hardware.
Table 11-1. Configuration of Watchdog Timer 2
Item Configuration
Control registers
Watchdog timer mode register 2 (WDTM2)
Watchdog timer enable register (WDTE)