Datasheet

V850ES/JG3 CHAPTER 3 CPU FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 25 of 870
Sep 30, 2010
CHAPTER 3 CPU FUNCTION
The CPU of the V850ES/JG3 is based on RISC architecture and executes almost all instructions with one clock by
using a 5-stage pipeline.
3.1 Features
Minimum instruction execution time: 31.25 ns (at 32 MHz operation)
30.5
μ s (with subclock (fXT) = 32.768 kHz operation)
Memory space Program (physical address) space: 64 MB linear
Data (logical address) space: 4 GB linear
General-purpose registers: 32 bits × 32 registers
Internal 32-bit architecture
5-stage pipeline control
Multiplication/division instruction
Saturation operation instruction
32-bit shift instruction: 1 clock
Load/store instruction with long/short format
Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1