Datasheet

V850ES/JG3 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM)
R01UH0015EJ0300 Rev.3.00 Page 383 of 870
Sep 30, 2010
9.4.2 Cautions
(1) It takes the 16-bit counter up to the following time to start counting after the TM0CTL0.TM0CE bit is set to 1,
depending on the count clock selected.
Selected Count Clock Maximum Time Before Counting Start
fXX 2/fXX
fXX/2 3/fXX
fXX/4 6/fXX
fXX/64 128/fXX
fXX/512 1024/fXX
INTWT Second rising edge of INTWT signal
fR/8 16/fR
fXT 2/fXT
(2) Rewriting the TM0CMP0 and TM0CTL0 registers is prohibited while TMM0 is operating.
If these registers are rewritten while the TM0CE bit is 1, the operation cannot be guaranteed.
If they are rewritten by mistake, clear the TM0CTL0.TM0CE bit to 0, and re-set the registers.