Datasheet

V850ES/JG3 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM)
R01UH0015EJ0300 Rev.3.00 Page 382 of 870
Sep 30, 2010
(2) Interval timer mode operation timing
Caution Do not set the TM0CMP0 register to FFFFH.
(a) Operation if TM0CMP0 register is set to 0000H
If the TM0CMP0 register is set to 0000H, the INTTM0EQ0 signal is generated at each count clock.
The value of the 16-bit counter is always 0000H.
Count clock
16-bit counter
TM0CE bit
TM0CMP0 register
INTTM0EQ0 signal
0000H
Interval time
Count clock cycle
FFFFH 0000H 0000H 0000H 0000H
Interval time
Count clock cycle
(b) Operation if TM0CMP0 register is set to N
If the TM0CMP0 register is set to N, the 16-bit counter counts up to N. The counter is cleared to 0000H in
synchronization with the next count-up timing and the INTTM0EQ0 signal is generated.
FFFFH
16-bit counter
0000H
TM0CE bit
TM0CMP0 register
INTTM0EQ0 signal
N
Interval time
(N + 1) ×
count clock cycle
Interval time
(N + 1) ×
count clock cycle
Interval time
(N + 1) ×
count clock cycle
N
Remark 0000H < N < FFFFH