Datasheet

V850ES/JG3 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM)

R01UH0015EJ0300 Rev.3.00 Page 381 of 870

Sep 30, 2010

(1) Interval timer mode operation flow

Figure 9-5. Software Processing Flow in Interval Timer Mode

FFFFH

16-bit counter

0000H

TM0CE bit

TM0CMP0 register

INTTM0EQ0 signal

D D D

<1> <2>

TM0CE bit = 1

TM0CE bit = 0

TM0CTL0 register

(TM0CKS0 to TM0CKS2 bits)

TM0CMP0 register

Initial setting of these registers is performed

before setting the TM0CE bit to 1.

Setting the TM0CKS0 to TM0CKS2 bits is

prohibited at the same time when counting

has been started (TM0CE bit = 1).

The counter is initialized and counting is

stopped by clearing the TM0CE bit to 0.

START

STOP

<1> Count operation start flow

<2> Count operation stop flow