Datasheet

V850ES/JG3 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM)
R01UH0015EJ0300 Rev.3.00 Page 380 of 870
Sep 30, 2010
Figure 9-4. Register Setting for Interval Timer Mode Operation
(a) TMM0 control register 0 (TM0CTL0)
0/1 0 0 0 0
TM0CTL0
0/1 0/1 0/1
TM0CKS2 TM0CKS1 TM0CKS0 TM0CE
0: Stop counting
1: Enable counting
Select count clock
(b) TMM0 compare register 0 (TM0CMP0)
If the TM0CMP0 register is set to D, the interval is as follows.
Interval = (D + 1) × Count clock cycle