Datasheet

V850ES/JG3 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM)
R01UH0015EJ0300 Rev.3.00 Page 379 of 870
Sep 30, 2010
9.4 Operation
Caution Do not set the TM0CMP0 register to FFFFH.
9.4.1 Interval timer mode
In the interval timer mode, an interrupt request signal (INTTM0EQ0) is generated at the specified interval if the
TM0CTL0.TM0CE bit is set to 1.
Figure 9-2. Configuration of Interval Timer
16-bit counter
TM0CMP0 registerTM0CE bit
Count clock
selection
Clear
Match signal
INTTM0EQ0 signal
Figure 9-3. Basic Timing of Operation in Interval Timer Mode
FFFFH
16-bit counter
0000H
TM0CE bit
TM0CMP0 register
INTTM0EQ0 signal
D
D D D D
Interval (D + 1) Interval (D + 1) Interval (D + 1) Interval (D + 1)
When the TM0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with
the count clock, and the counter starts counting.
When the count value of the 16-bit counter matches the value of the TM0CMP0 register, the 16-bit counter is cleared to
0000H and a compare match interrupt request signal (INTTM0EQ0) is generated.
The interval can be calculated by the following expression.
Interval = (Set value of TM0CMP0 register + 1) × Count clock cycle