Datasheet

V850ES/JG3 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM)
R01UH0015EJ0300 Rev.3.00 Page 378 of 870
Sep 30, 2010
9.3 Register
(1) TMM0 control register (TM0CTL0)
The TM0CTL0 register is an 8-bit register that controls the TMM0 operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The same value can always be written to the TM0CTL0 register by software.
TM0CE
TMM0 operation disabled (16-bit counter reset asynchronously).
Operation clock application stopped.
TMM0 operation enabled. Operation clock application started. TMM0
operation started.
TM0CE
0
1
Internal clock operation enable/disable specification
TM0CTL0
0 0 0 0 TM0CKS2 TM0CKS1 TM0CKS0
654321
After reset: 00H R/W Address: FFFFF690H
The internal clock control and internal circuit reset for TMM0 are performed
asynchronously with the TM0CE bit. When the TM0CE bit is cleared to 0, the
internal clock of TMM0 is disabled (fixed to low level) and 16-bit counter is reset
asynchronously.
<7> 0
f XX
f XX /2
f
XX /4
f
XX /64
f
XX /512
INTWT
f R /8
f
XT
TM0CKS2
0
0
0
0
1
1
1
1
Count clock selectionTM0CKS1
0
0
1
1
0
0
1
1
TM0CKS0
0
1
0
1
0
1
0
1
Cautions 1. Set the TM0CKS2 to TM0CKS0 bits when TM0CE bit = 0.
When changing the value of TM0CE from 0 to 1, it is not possible to set
the value of the TM0CKS2 to TM0CKS0 bits simultaneously.
2. Be sure to clear bits 3 to 6 to “0”.
Remark f
XX: Main clock frequency
f
R: Internal oscillation clock frequency
f
XT: Subclock frequency