Datasheet

V850ES/JG3 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM)
R01UH0015EJ0300 Rev.3.00 Page 377 of 870
Sep 30, 2010
9.2 Configuration
TMM0 includes the following hardware.
Table 9-1. Configuration of TMM0
Item Configuration
Timer register 16-bit counter
Register TMM0 compare register 0 (TM0CMP0)
Control register TMM0 control register 0 (TM0CTL0)
Figure 9-1. Block Diagram of TMM0
TM0CTL0
Internal bus
f XX
f XX /2
f
XX /4
f
XX /64
f
XX /512
INTWT
f
R /8
f
XT
Controller
16-bit counter
Match
Clear
INTTM0EQ0
TM0CMP0
TM0CE TM0CKS2 TM0CKS1TM0CKS0
Selector
Remark f
XX: Main clock frequency
f
R: Internal oscillation clock frequency
f
XT: Subclock frequency
INTWT: Watch timer interrupt request signal
(1) 16-bit counter
This is a 16-bit counter that counts the internal clock.
The 16-bit counter cannot be read or written.
(2) TMM0 compare register 0 (TM0CMP0)
The TM0CMP0 register is a 16-bit compare register.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
The same value can always be written to the TM0CMP0 register by software.
TM0CMP0 register rewrite is prohibited when the TM0CTL0.TM0CE bit = 1.
TM0CMP0
12 10 8 6 4 2
After reset: 0000H R/W Address: FFFFF694H
14 0
13 11 9 7 5 3
15 1