Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 375 of 870
Sep 30, 2010
8.6 Cautions
(1) Capture operation
When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be
captured in the TQ0CCR0, TQ0CCR1, TQ0CCR2, and TQ0CCR3 registers if the capture trigger is input
immediately after the TQ0CE bit is set to 1.
(a) Free-running timer mode
Count clock
0000H
FFFFH
TQ0CE bit
TQ0CCR0 register
FFFFH 0001H0000H
TIQ00 pin input
Capture
trigger input
16-bit counter
Sampling clock (f
XX )
Capture
trigger input
(b) Pulse width measurement mode
0000H
FFFFH
FFFFH 0002H0000H
Count clock
TQ0CE bit
TQ0CCR0 register
TIQ00 pin input
Capture
trigger input
16-bit counter
Sampling clock (f
XX)
Capture
trigger input