Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 373 of 870
Sep 30, 2010
(2) Operation timing in pulse width measurement mode
(a) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TQ0OVF bit to 0 with the CLR instruction and by writing 8-
bit data (bit 0 is “0”) to the TQ0OPT0 register. To accurately detect an overflow, read the TQ0OVF bit when it is
1, and then clear the overflow flag by using a bit manipulation instruction.
(i) Operation to write 0 (without conflict with setting) (iii) Operation to clear to 0 (without conflict with setting)
(ii) Operation to write 0 (conflict with setting) (iv) Operation to clear to 0 (conflict with setting)
0 write signal
Overflow
set signal
Register
access signal
Overflow flag
(TQ0OVF bit)
Read Write
0 write signal
Overflow
set signal
Register
access signal
Overflow flag
(TQ0OVF bit)
Read Write
0 write signal
Overflow
set signal
0 write signal
Overflow
set signal
Overflow flag
(TQ0OVF bit)
Overflow flag
(TQ0OVF bit)
L
H
L
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow
may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has
occurred even when an overflow actually has occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to
0 with the CLR instruction, the overflow flag remains set even after execution of the clear instruction.