Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 368 of 870
Sep 30, 2010
8.5.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110)
In the pulse width measurement mode, 16-bit timer/event counter Q starts counting when the TQ0CTL0.TQ0CE bit is
set to 1. Each time the valid edge input to the TIQ0m pin has been detected, the count value of the 16-bit counter is stored
in the TQ0CCRm register, and the 16-bit counter is cleared to 0000H.
The interval of the valid edge can be measured by reading the TQ0CCRm register after a capture interrupt request
signal (INTTQ0CCm) occurs.
Select either of the TIQ00 to TIQ03 pins as the capture trigger input pin. Specify “No edge detected” by using the
TQ0IOC1 register for the unused pins.
Remark m = 0 to 3
k = 1 to 3
Figure 8-34. Configuration in Pulse Width Measurement Mode
INTTQ0OV signal
INTTQ0CC0 signal
INTTQ0CC1 signal
INTTQ0CC2 signal
INTTQ0CC3 signal
TIQ03 pin
(capture
trigger input)
TQ0CCR3
register
(capture)
TIQ00 pin
(external
event count
input/capture
trigger input)
Internal count clock
TQ0CE
bit
TIQ01 pin
(capture
trigger input)
TIQ02 pin
(capture
trigger input)
TQ0CCR0
register
(capture)
TQ0CCR1
register
(capture)
TQ0CCR2
register
(capture)
16-bit counter
Clear
Edge
detector
Edge
detector
Edge
detector
Edge
detector
Edge
detector
Count
clock
selection