Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 366 of 870
Sep 30, 2010
Example when capture trigger interval is long
FFFFH
16-bit counter
0000H
TQ0CE bit
TIQ0m pin input
TQ0CCRm register
INTTQ0OV signal
TQ0OVF bit
Overflow
counter
Note
Dm0 Dm1
1H0H 2H 0H
Dm0
Dm1
<1> <2> <3> <4>
1 cycle of 16-bit counter
Pulse width
Note The overflow counter is set arbitrarily by software on the internal RAM.
<1> Read the TQ0CCRm register (setting of the default value of the TIQ0m pin input).
<2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow
interrupt servicing.
<3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag to
0 in the overflow interrupt servicing.
<4> Read the TQ0CCRm register.
Read the overflow counter.
→ When the overflow counter is “N”, the pulse width can be calculated by (N × 10000H + D
m1 –
D
m0).
In this example, the pulse width is (20000H + D
m1 – Dm0) because an overflow occurs twice.
Clear the overflow counter (0H).