Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 364 of 870
Sep 30, 2010
(2/2)
Example when two capture registers are used (without using overflow interrupt)
FFFFH
16-bit counter
0000H
TQ0CE bit
INTTQ0OV signal
TQ0OVF bit
TQ0OVF0 flag
Note
TIQ00 pin input
TQ0CCR0 register
TQ0OVF1 flag
Note
TIQ01 pin input
TQ0CCR1 register
D 10
D 11
D 00
D 01
D 10
<1> <2> <5> <6><3> <4>
D 00
D 11
D 01
Note The TQ0OVF0 and TQ0OVF1 flags are set on the internal RAM by software.
<1> Read the TQ0CCR0 register (setting of the default value of the TIQ00 pin input).
<2> Read the TQ0CCR1 register (setting of the default value of the TIQ01 pin input).
<3> An overflow occurs. Nothing is done by software.
<4> Read the TQ0CCR0 register.
Read the overflow flag. If the overflow flag is 1, set only the TQ0OVF1 flag to 1, and clear the
overflow flag to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
01 − D00).
<5> Read the TQ0CCR1 register.
Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read.
Read the TQ0OVF1 flag. If the TQ0OVF1 flag is 1, clear it to 0.
Because the TQ0OVF1 flag is 1, the pulse width can be calculated by (10000H + D
11 − D10)
(correct).
<6> Same as <3>