Datasheet
V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 358 of 870
Sep 30, 2010
(2) Operation timing in free-running timer mode
(a) Interval operation with compare register
When 16-bit timer/event counter Q is used as an interval timer with the TQ0CCRm register used as a compare
register, software processing is necessary for setting a comparison value to generate the next interrupt request
signal each time the INTTQ0CCm signal has been detected.
D
00
D
10
D
20
D
01
D
30
D
12
D
03
D
22
D
31
D
21
D
23
D
02
D
13
FFFFH
16-bit counter
0000H
TQ0CE bit
TQ0CCR0 register
INTTQ0CC0 signal
TOQ00 pin output
TQ0CCR1 register
INTTQ0CC1 signal
TOQ01 pin output
TQ0CCR2 register
INTTQ0CC2 signal
TOQ02 pin output
TQ0CCR3 register
INTTQ0CC3 signal
TOQ03 pin output
Interval period
(D
00
+ 1)
Interval period
(10000H +
D
02
− D
01
)
Interval period
(D
01
− D
00
)
Interval period
(D
03
− D
02
)
Interval period
(D
04
− D
03
)
D
00
D
01
D
02
D
03
D
04
D
05
Interval period
(D
10
+ 1)
Interval period
(10000H + D
12
− D
11
)
Interval period
(D
11
− D
10
)
Interval period
(D
13
− D
12
)
D
10
D
11
D
12
D
13
D
14
Interval period
(D
20
+ 1)
Interval period
(10000H + D
21
− D
20
)
Interval period
(10000H + D
23
− D
22
)
Interval period
(D
22
− D
21
)
Interval period
(D
30
+ 1)
Interval period
(10000H + D
31
− D
30)
D
20
D
21
D
22
D
23
D
31
D
30
D
32
D
04
D
11