Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)

R01UH0015EJ0300 Rev.3.00 Page 357 of 870

Sep 30, 2010

Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2)

TQ0CE bit = 1

Read TQ0OPT0 register

(check overflow flag).

TQ0CTL0 register

(TQ0CKS0 to TQ0CKS2 bits)

TQ0CTL1 register,

TQ0IOC1 register,

TQ0OPT0 register

Initial setting of these registers

is performed before setting the

TQ0CE bit to 1.

The TQ0CKS0 to TQ0CKS2 bits can

be set at the same time when counting

has been started (TQ0CE bit = 1).

START

Execute instruction to clear

TQ0OVF bit (CLR TQ0OVF).

<1> Count operation start flow

<2> Overflow flag clear flow

TQ0CE bit = 0

Counter is initialized and

counting is stopped by

clearing TQ0CE bit to 0.

STOP

<3> Count operation stop flow

TQ0OVF bit = 1

YES