Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 356 of 870
Sep 30, 2010
(b) When using capture/compare register as capture register
Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2)
D 20
D 00
D 30
D 10
D 11
D 21
D 31
D 12 D 01
D 02
D 22
D 32
D 03
D 13
D 33
D 23
0000 D 00 D 01 D 02 D 03 0000
0000
0000
0000
0000 D 10 D 11 D 12 D 13
0000 D 20 D 21 D 23 D 22
0000 D 30 D 31 D 32 D 33
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
<3><1>
<2> <2> <2>
FFFFH
16-bit counter
0000H
TQ0CE bit
TIQ02 pin input
TQ0CCR2 register
INTTQ0CC2 signal
TIQ03 pin input
TQ0CCR3 register
INTTQ0CC3 signal
INTTQ0OV signal
TQ0OVF bit
TIQ01 pin input
TQ0CCR1 register
INTTQ0CC1 signal
TIQ00 pin input
TQ0CCR0 register
INTTQ0CC0 signal