Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 354 of 870
Sep 30, 2010
(1) Operation flow in free-running timer mode
(a) When using capture/compare register as compare register
Figure 8-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2)
D10
D20
D30
D00
D10
D20
D30
D00
D11
D31
D01
D21 D21
D11
D11
D31
D01
FFFFH
16-bit counter
0000H
TQ0CE bit
TQ0CCR0 register
INTTQ0CC0 signal
TOQ00 pin output
TQ0CCR1 register
INTTQ0CC1 signal
TOQ01 pin output
TQ0CCR2 register
INTTQ0CC2 signal
TOQ02 pin output
TQ0CCR3 register
INTTQ0CC3 signal
TOQ03 pin output
INTTQ0OV signal
TQ0OVF bit
D00
D10
D20
D30
D01
D11
D21
D31
Cleared to 0 by
CLR instruction
Set value changed
Set value changed
Set value changed
Set value changed
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
<3><1>
<2> <2> <2>