Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 353 of 870
Sep 30, 2010
Figure 8-31. Register Setting in Free-Running Timer Mode (3/3)
(e) TMQ0 I/O control register 2 (TQ0IOC2)
0 0 0 0 0/1
TQ0IOC2
Select valid edge of
external event count input
0/1 0 0
TQ0EES0 TQ0ETS1 TQ0ETS0TQ0EES1
(f) TMQ0 option register 0 (TQ0OPT0)
0/1 0/1 0/1 0/1 0
TQ0OPT0
Overflow flag
Specifies if TQ0CCR0
register functions as
capture or compare register
Specifies if TQ0CCR1
register functions as
capture or compare register
0 0 0/1
TQ0CCS0 TQ0OVFTQ0CCS1
TQ0CCS2TQ0CCS3
Specifies if TQ0CCR2
register functions as
capture or compare register
Specifies if TQ0CCR3
register functions as
capture or compare register
(g) TMQ0 counter read buffer register (TQ0CNT)
The value of the 16-bit counter can be read by reading the TQ0CNT register.
(h) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3)
These registers function as capture registers or compare registers depending on the setting of the
TQ0OPT0.TQ0CCSm bit.
When the registers function as capture registers, they store the count value of the 16-bit counter when
the valid edge input to the TIQ0m pin is detected.
When the registers function as compare registers and when D
m is set to the TQ0CCRm register, the
INTTQ0CCm signal is generated when the counter reaches (Dm + 1), and the output signal of the TOQ0m
pin is inverted.
Remark m = 0 to 3