Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 352 of 870
Sep 30, 2010
Figure 8-31. Register Setting in Free-Running Timer Mode (2/3)
(c) TMQ0 I/O control register 0 (TQ0IOC0)
0/1 0/1 0/1 0/1 0/1
TQ0IOC0
0: Disable TOQ00 pin output
1: Enable TOQ00 pin output
0: Disable TOQ01 pin output
1: Enable TOQ01 pin output
Setting of output level with
operation of TOQ01 pin
disabled
0: Low level
1: High level
0/1 0/1 0/1
TQ0OE1 TQ0OL0 TQ0OE0TQ0OL1
TQ0OE3 TQ0OL2 TQ0OE2TQ0OL3
Setting of output level with
operation of TOQ03 pin
disabled
0: Low level
1: High level
0: Disable TOQ02 pin output
1: Enable TOQ02 pin output
Setting of output level with
operation of TOQ02 pin
disabled
0: Low level
1: High level
0: Disable TOQ03 pin output
1: Enable TOQ03 pin output
Setting of output level with
operation of TOQ00 pin disabled
0: Low level
1: High level
(d) TMQ0 I/O control register 1 (TQ0IOC1)
0/1 0/1 0/1 0/1 0/1
TQ0IOC1
Select valid edge
of TIQ00 pin input
Select valid edge
of TIQ01 pin input
0/1 0/1 0/1
TQ0IS2 TQ0IS1 TQ0IS0TQ0IS3
TQ0IS6 TQ0IS5 TQ0IS4TQ0IS7
Select valid edge
of TIQ02 pin input
Select valid edge
of TIQ03 pin input