Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 351 of 870
Sep 30, 2010
Figure 8-31. Register Setting in Free-Running Timer Mode (1/3)
(a) TMQ0 control register 0 (TQ0CTL0)
0/1 0 0 0 0
TQ0CTL0
Select count clock
Note
0: Stop counting
1: Enable counting
0/1 0/1 0/1
TQ0CKS2 TQ0CKS1 TQ0CKS0TQ0CE
Note The setting is invalid when the TQ0CTL1.TQ0EEE bit = 1
(b) TMQ0 control register 1 (TQ0CTL1)
0 0 0/1 0 0
TQ0CTL1
101
TQ0MD2 TQ0MD1 TQ0MD0TQ0EEETQ0EST
1, 0, 1:
Free-running mode
0: Operate with count
clock selected by
TQ0CKS0 to TQ0CKS2 bits
1: Count on external
event count input signal