Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 350 of 870
Sep 30, 2010
When the TQ0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQ0m pin is
detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, and a capture interrupt request signal
(INTTQ0CCm) is generated.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTQ0OV) at the next clock, is cleared to 0000H, and continues counting.
At this time, the overflow flag (TQ0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by
software.
Figure 8-30. Basic Timing in Free-Running Timer Mode (Capture Function)
D20
D00
D30
D10
D11
D21
D31
D12D01
D02
D22
D32
D03
D13
D33
D23
0000 D00 D01 D02 D03
0000 D10 D11 D12 D13
0000 D20 D21 D23D22
0000 D30 D31 D32 D33
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
FFFFH
16-bit counter
0000H
TIQ02 pin input
TQ0CCR2 register
INTTQ0CC2 signal
TIQ03 pin input
TQ0CCR3 register
INTTQ0CC3 signal
INTTQ0OV signal
TQ0OVF bit
TIQ01 pin input
TQ0CCR1 register
INTTQ0CC1 signal
TQ0CE bit
TIQ00 pin input
TQ0CCR0 register
INTTQ0CC0 signal