Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 349 of 870
Sep 30, 2010
When the TQ0CE bit is set to 1, 16-bit timer/event counter Q starts counting, and the output signals of the TOQ00 to
TOQ03 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TQ0CCRm register,
a compare match interrupt request signal (INTTQ0CCm) is generated, and the output signal of the TOQ0m pin is inverted.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTQ0OV) at the next clock, is cleared to 0000H, and continues counting.
At this time, the overflow flag (TQ0OPT0.TQ0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR
instruction by software.
The TQ0CCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at
that time, and compared with the count value.
Figure 8-29. Basic Timing in Free-Running Timer Mode (Compare Function)
D10
D20
D30
D00
D20 D31 D31
D30
D00
D11D11
D21
D01
D11
D21
D01
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
FFFFH
16-bit counter
0000H
TOQ01 pin output
TQ0CCR2 register
INTTQ0CC2 signal
TOQ02 pin output
TQ0CCR3 register
INTTQ0CC3 signal
TOQ03 pin output
INTTQ0OV signal
TQ0OVF bit
TOQ00 pin output
TQ0CCR1 register
INTTQ0CC1 signal
TQ0CE bit
TQ0CCR0 register
INTTQ0CC0 signal
D00 D01
D11D10
D21D20
D31D30