Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 348 of 870
Sep 30, 2010
8.5.6 Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101)
In the free-running timer mode, 16-bit timer/event counter Q starts counting when the TQ0CTL0.TQ0CE bit is set to 1.
At this time, the TQ0CCRm register can be used as a compare register or a capture register, depending on the setting of
the TQ0OPT0.TQ0CCS0 and TQ0OPT0.TQ0CCS1 bits.
Remark m = 0 to 3
Figure 8-28. Configuration in Free-Running Timer Mode
TOQ03 pin output
TOQ02 pin output
TOQ01 pin output
TOQ00 pin output
INTTQ0OV signal
TQ0CCS0,
TQ0CCS1 bits
(capture/compare
selection)
INTTQ0CC3 signal
INTTQ0CC2 signal
INTTQ0CC1 signal
INTTQ0CC0 signal
TIQ03 pin
(capture
trigger input)
TQ0CCR3
register
(capture)
TIQ00 pin
(external event
count input/
capture
trigger input)
Internal count clock
TQ0CE
bit
TIQ01 pin
(capture
trigger input)
TIQ02 pin
(capture
trigger input)
TQ0CCR0
register
(capture)
TQ0CCR1
register
(capture)
TQ0CCR2
register
(capture)
TQ0CCR3
register
(compare)
TQ0CCR2
register
(compare)
TQ0CCR1
register
(compare)
0
1
0
1
0
1
0
1
16-bit counter
TQ0CCR0
register
(compare)
Output
controller
Output
controller
Output
controller
Output
controller
Count
clock
selection
Edge
detector
Edge
detector
Edge
detector
Edge
detector
Edge
detector