Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 341 of 870
Sep 30, 2010
Figure 8-26. Register Setting for Operation in PWM Output Mode (3/3)
(f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3)
If D
0 is set to the TQ0CCR0 register and Dk to the TQ0CCR1 register, the cycle and active level of the
PWM waveform are as follows.
Cycle = (D
0 + 1) × Count clock cycle
Active level width = D
k × Count clock cycle
Remarks 1. TMQ0 I/O control register 1 (TQ0IOC1) and TMQ0 option register 0 (TQ0OPT0) are not
used in the PWM output mode.
2. Updating the TMQ0 capture/compare register 2 (TQ0CCR2) and TMQ0 capture/compare
register 3 (TQ0CCR3) is validated by writing the TMQ0 capture/compare register 1
(TQ0CCR1).