Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 336 of 870
Sep 30, 2010
(b) Generation timing of compare match interrupt request signal (INTTQ0CCk)
The generation timing of the INTTQ0CCk signal in the one-shot pulse output mode is different from other
INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches
the value of the TQ0CCRk register.
Count clock
16-bit counter
TQ0CCRk register
TOQ0k pin output
INTTQ0CCk signal
D k
D k − 2D k − 1D k D k + 1 D k + 2
Usually, the INTTQ0CCk signal is generated when the 16-bit counter counts up next time after its count value
matches the value of the TQ0CCRk register.
In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is
changed to match the change timing of the TOQ0k pin.
Remark k = 1 to 3