Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 335 of 870
Sep 30, 2010
(2) Operation timing in one-shot pulse output mode
(a) Note on rewriting TQ0CCRm register
To change the set value of the TQ0CCRm register to a smaller value, stop counting once, and then change the
set value.
If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
D k0
D k1
D 01
D 01 D 00
D k1
D 01
D k0
D k0 D k1
D 00 D 00
FFFFH
16-bit counter
0000H
TQ0CE bit
External trigger input
(TIQ00 pin input)
TQ0CCR0 register
INTTQ0CC0 signal
TOQ00 pin output
(only when software
trigger is used)
TQ0CCRk register
INTTQ0CCk signal
TOQ0k pin output
Delay
(D
k0 )
Active level width
(D
00 − D k0 + 1)
Active level width
(D 01 − D k1 + 1)
Active level width
(D 01 − D k1 + 1)
Delay
(D
k1 )
Delay
(10000H + D k1 )
When the TQ0CCR0 register is rewritten from D
00 to D01 and the TQ0CCRk register from Dk0 to Dk1 where D00
> D
01 and Dk0 > Dk1, if the TQ0CCRk register is rewritten when the count value of the 16-bit counter is greater
than D
k1 and less than Dk0 and if the TQ0CCR0 register is rewritten when the count value is greater than D01
and less than D
00, each set value is reflected as soon as the register has been rewritten and compared with the
count value. The counter counts up to FFFFH and then counts up again from 0000H. When the count value
matches D
k1, the counter generates the INTTQ0CCk signal and asserts the TOQ0k pin. When the count value
matches D
01, the counter generates the INTTQ0CC0 signal, deasserts the TOQ0k pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the one-
shot pulse that is originally expected.
Remark k = 1 to 3