Datasheet

V850ES/JG3 CHAPTER 2 PIN FUNCTIONS
R01UH0015EJ0300 Rev.3.00 Page 19 of 870
Sep 30, 2010
2.2 Pin States
The operation states of pins in the various modes are described below.
Table 2-2. Pin Operation States in Various Modes
Pin Name
When Power
Is Turned
On
Note 1
During Reset
(Except When
Power Is Turned On)
HALT
Mode
Note 2
IDLE1,
IDLE2,
Sub-IDLE
Mode
Note 2
STOP
Mode
Note 2
Idle
State
Note 3
Bus Hold
P05/DRST Pulled down Pulled down
Note 4
Held Held Held Held Held
P10/ANO0, P11/ANO1 Hi-Z Hi-Z Held Held Hi-Z Held Held
P53/DDO Undefined Hi-Z
Note 5
Held Held Held Held Held
AD0 to AD15 Notes 7, 8
A0 to A15 Undefined
Notes 7, 9
A16 to A21 Undefined
Note 7
Hi-Z Hi-Z Held Hi-Z
WAIT
− − − − −
CLKOUT Operating L L Operating Operating
WR0, WR1
RD
ASTB
H
Note 7
Hi-Z
HLDAK
H H H
L
HLDRQ
Hi-Z
Note 6
Hi-Z
Note 6
Operating
Note 7
− − −
Operating
Other port pins Hi-Z Hi-Z Held Held Held Held Held
Notes 1. Duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower limit)
when the power is turned on.
2. Operates while alternate functions are operating.
3. In separate bus mode, the state of the pins in the idle state inserted after the T2 state is shown. In
multiplexed bus mode, the state of the pins in the idle state inserted after the T3 state is shown.
4. Pulled down during external reset. During internal reset by the watchdog timer, clock monitor, etc., the state
of this pin differs according to the OCDM.OCDM0 bit setting.
5. DDO output is specified in the on-chip debug mode.
6. The bus control pins function alternately as port pins, so they are initialized to the input mode (port mode).
7. Operates even in the HALT mode, during DMA operation.
8. In separate bus mode: Hi-Z
In multiplexed bus mode: Undefined
9. In separate bus mode
Remark Hi-Z: High impedance
Held: The state during the immediately preceding external bus cycle is held.
L: Low-level output
H: High-level output
−: Input without sampling (not acknowledged)