Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 332 of 870
Sep 30, 2010
Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (3/3)
(f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3)
If D
0 is set to the TQ0CCR0 register and Dk to the TQ0CCRk register, the active level width and output
delay period of the one-shot pulse are as follows.
Active level width = (D
0 − Dk + 1) × Count clock cycle
Output delay period = (Dk) × Count clock cycle
Caution One-shot pulses are not output even in the one-shot pulse output mode, if the value set
in the TQ0CCRk register is greater than that set in the TQ0CCR0 register.
Remarks 1. TMQ0 I/O control register 1 (TQ0IOC1) and TMQ0 option register 0 (TQ0OPT0) are not
used in the one-shot pulse output mode.
2. k = 1 to 3