Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 330 of 870
Sep 30, 2010
When the TQ0CE bit is set to 1, 16-bit timer/event counter Q waits for a trigger. When the trigger is generated, the 16-
bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOQ0k pin. After the
one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is
generated again while the one-shot pulse is being output, it is ignored.
The output delay period and active level width of the one-shot pulse can be calculated as follows.
Output delay period = (Set value of TQ0CCRk register) × Count clock cycle
Active level width = (Set value of TQ0CCR0 register − Set value of TQ0CCRk register + 1) × Count clock cycle
The compare match interrupt request signal INTTQ0CC0 is generated when the 16-bit counter counts after its count
value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTQ0CCk is
generated when the count value of the 16-bit counter matches the value of the CCRk buffer register.
The valid edge of an external trigger input or setting the software trigger (TQ0CTL1.TQ0EST bit) to 1 is used as the
trigger.
Remark k = 1 to 3
Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (1/3)
(a) TMQ0 control register 0 (TQ0CTL0)
0/1 0 0 0 0
TQ0CTL0
Select count clock
0: Stop counting
1: Enable counting
0/1 0/1 0/1
TQ0CKS2 TQ0CKS1 TQ0CKS0TQ0CE
(b) TMQ0 control register 1 (TQ0CTL1)
0 0/1 0 0 0
TQ0CTL1
Generate software trigger
when 1 is written
011
TQ0MD2 TQ0MD1 TQ0MD0TQ0EEETQ0EST
0, 1, 1:
One-shot pulse output mode