Datasheet

V850ES/JG3 CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 328 of 870
Sep 30, 2010
8.5.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011)
In the one-shot pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set
to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter Q starts counting, and outputs
a one-shot pulse from the TOQ01 to TOQ03 pins.
Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software trigger
is used, the TOQ00 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter
is stopped (waiting for a trigger).
Figure 8-20. Configuration in One-Shot Pulse Output Mode
CCR0 buffer register
TQ0CE bit
TQ0CCR0 register
Clear
Match signal
INTTQ0CC0 signal
TOQ03 pin
INTTQ0CC3 signal
TOQ00 pin
TIQ00 pin
Transfer
S
R
S
R
TQ0CCR1
register
CCR1 buffer
register
Match signal
TOQ01 pin
INTTQ0CC1 signal
Transfer
Transfer
S
R
TQ0CCR3
register
CCR3 buffer
register
Match signal
Transfer
TOQ02 pin
INTTQ0CC2 signal
S
R
TQ0CCR2
register
CCR2 buffer
register
Match signal
16-bit counter
Count clock
selection
Count start
control
Edge
detector
Software trigger
generation
Output
controller
(RS-FF)
Output
controller
(RS-FF)
Output
controller
(RS-FF)
Output
controller
(RS-FF)