Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 327 of 870
Sep 30, 2010
(e) Generation timing of compare match interrupt request signal (INTTQ0CCk)
The timing of generation of the INTTQ0CCk signal in the external trigger pulse output mode differs from the
timing of other INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit
counter matches the value of the CCRk buffer register.
Count clock
16-bit counter
CCRk buffer register
TOQ0k pin output
INTTQ0CCk signal
Dk
Dk − 2Dk − 1Dk Dk + 1 Dk + 2
Remark k = 1 to 3
Usually, the INTTQ0CCk signal is generated in synchronization with the next count up after the count value of
the 16-bit counter matches the value of the CCRk buffer register.
In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing
is changed to match the timing of changing the output signal of the TOQ0k pin.