Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 326 of 870
Sep 30, 2010
(d) Conflict between trigger detection and match with CCR0 buffer register
If the trigger is detected immediately after the INTTQ0CC0 signal is generated, the 16-bit counter is cleared to
0000H and continues counting up. Therefore, the active period of the TOQ0k pin is extended by time from
generation of the INTTQ0CC0 signal to trigger detection.
16-bit counter
CCR0 buffer register
INTTQ0CC0 signal
TOQ0k pin output
External trigger input
(TIQ00 pin input)
D0
D0 − 1D00000FFFF 0000 0000
Extended
Remark k = 1 to 3
If the trigger is detected immediately before the INTTQ0CC0 signal is generated, the INTTQ0CC0 signal is not
generated. The 16-bit counter is cleared to 0000H, the TOQ0k pin is asserted, and the counter continues
counting. Consequently, the inactive period of the PWM waveform is shortened.
16-bit counter
CCR0 buffer register
INTTQ0CC0 signal
TOQ0k pin output
External trigger input
(TIQ00 pin input)
D0
D0 − 1D00000FFFF 0000 0001
Shortened
Remark k = 1 to 3