Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 324 of 870
Sep 30, 2010
(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TQ0CCRk register to 0000H. If the set value of the TQ0CCR0 register is
FFFFH, the INTTQ0CCk signal is generated periodically.
Count clock
16-bit counter
TQ0CE bit
TQ0CCR0 register
TQ0CCRk register
INTTQ0CC0 signal
INTTQ0CCk signal
TOQ0k pin output
D 0
0000H
D
0
0000H
D
0
0000H
D 0 − 1D 0 0000FFFF 0000 D 0 − 1D 0 00000001
L
Remark k = 1 to 3
To output a 100% waveform, set a value of (set value of TQ0CCR0 register + 1) to the TQ0CCRk register. If
the set value of the TQ0CCR0 register is FFFFH, 100% output cannot be produced.
Count clock
16-bit counter
TQ0CE bit
TQ0CCR0 register
TQ0CCRk register
INTTQ0CC0 signal
INTTQ0CCk signal
TOQ0k pin output
D 0
D 0 + 1
D
0
D 0 + 1
D
0
D 0 + 1
D 0 − 1D 0 0000FFFF 0000 D 0 − 1D 0 00000001
Remark k = 1 to 3