Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 322 of 870
Sep 30, 2010
(2) External trigger pulse output mode operation timing
(a) Note on changing pulse width during operation
To change the PWM waveform while the counter is operating, write the TQ0CCR1 register last.
Rewrite the TQ0CCRk register after writing the TQ0CCR1 register after the INTTQ0CC0 signal is detected.
FFFFH
16-bit counter
0000H
TQ0CE bit
External trigger input
(TIQ00 pin input)
D 30
D 00
D 01
D 30 D 30
D 20 D 20 D 20
D 21
D 11
D 00 D 00 D 31
D 01 D 01
D 21
D 11
D 31
TQ0CCR0 register
CCR0 buffer register
INTTQ0CC0 signal
TQ0CCR1 register
CCR1 buffer register
INTTQ0CC1 signal
TOQ01 pin output
TQ0CCR2 register
CCR2 buffer register
INTTQ0CC2 signal
TOQ02 pin output
TQ0CCR3 register
CCR3 buffer register
INTTQ0CC3 signal
TOQ03 pin output
TOQ00 pin output
(only when software
trigger is used)
D 10 D 10 D 10
D 00
D 11
D 10 D 11
D 10
D 21
D 20 D 21
D 20
D 31
D 30 D 31
D 30
D 00 D 01