Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 319 of 870
Sep 30, 2010
Figure 8-18. Register Setting for Operation in External Trigger Pulse Output Mode (3/3)
(d) TMQ0 I/O control register 2 (TQ0IOC2)
00000
TQ0IOC2
Select valid edge of
external trigger input
0 0/1 0/1
TQ0EES0 TQ0ETS1 TQ0ETS0TQ0EES1
(e) TMQ0 counter read buffer register (TQ0CNT)
The value of the 16-bit counter can be read by reading the TQ0CNT register.
(f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3)
If D
0 is set to the TQ0CCR0 register, D1 to the TQ0CCR1 register, D2 to the TQ0CCR2 register, and D3, to
the TQ0CCR3 register, the cycle and active level of the PWM waveform are as follows.
Cycle = (D
0 + 1) × Count clock cycle
TOQ01 pin PWM waveform active level width = D
1 × Count clock cycle
TOQ02 pin PWM waveform active level width = D2 × Count clock cycle
TOQ03 pin PWM waveform active level width = D
3 × Count clock cycle
Remarks 1. TMQ0 I/O control register 1 (TQ0IOC1) and TMQ0 option register 0 (TQ0OPT0) are not
used in the external trigger pulse output mode.
2. Updating TMQ0 capture/compare register 2 (TQ0CCR2) and TMQ0 capture/compare register
3 (TQ0CCR3) is validated by writing TMQ0 capture/compare register 1 (TQ0CCR1).