Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 318 of 870
Sep 30, 2010
Figure 8-18. Register Setting for Operation in External Trigger Pulse Output Mode (2/3)
(b) TMQ0 control register 1 (TQ0CTL1)
00000
TQ0CTL1
Generate software trigger
when 1 is written
010
TQ0MD2 TQ0MD1 TQ0MD0TQ0EEETQ0EST
0, 1, 0:
External trigger pulse
output mode
(c) TMQ0 I/O control register 0 (TQ0IOC0)
0/1 0/1 0/1 0/1 0/1
TQ0IOC0
0: Disable TOQ00 pin output
1: Enable TOQ00 pin output
Setting of output level while
operation of TOQ00 pin is disabled
0: Low level
1: High level
0: Disable TOQ01 pin output
1: Enable TOQ01 pin output
Specification of active level
of TOQ01 pin output
0: Active-high
1: Active-low
0/1 0/1
Note
0/1
Note
TQ0OE1 TQ0OL0 TQ0OE0TQ0OL1
TOQ0k pin output
16-bit counter
• When TQ0OLk bit = 0
TOQ0k pin output
16-bit counter
• When TQ0OLk bit = 1
TQ0OE3 TQ0OL2 TQ0OE2TQ0OL3
Specification of active level
of TOQ03 pin output
0: Active-high
1: Active-low
0: Disable TOQ02 pin output
1: Enable TOQ02 pin output
Specification of active level
of TOQ02 pin output
0: Active-high
1: Active-low
0: Disable TOQ03 pin output
1: Enable TOQ03 pin output
Note Clear this bit to 0 when the TOQ00 pin is not used in the external trigger pulse output mode.