Datasheet

V850ES/JG3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R01UH0015EJ0300 Rev.3.00 Page 317 of 870
Sep 30, 2010
pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The
output of the TOQ00 pin is inverted. The TOQ0k pin outputs a high-level regardless of the status (high/low) when a trigger
is generated.)
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TQ0CCRk register) × Count clock cycle
Cycle = (Set value of TQ0CCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TQ0CCRk register)/(Set value of TQ0CCR0 register + 1)
The compare match request signal INTTQ0CC0 is generated when the 16-bit counter counts next time after its count
value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match
interrupt request signal INTTQ0CCk is generated when the count value of the 16-bit counter matches the value of the
CCRk buffer register.
The value set to the TQ0CCRm register is transferred to the CCRm buffer register when the count value of the 16-bit
counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H.
The valid edge of an external trigger input signal, or setting the software trigger (TQ0CTL1.TQ0EST bit) to 1 is used as
the trigger.
Remark k = 1 to 3, m = 0 to 3
Figure 8-18. Register Setting for Operation in External Trigger Pulse Output Mode (1/3)
(a) TMQ0 control register 0 (TQ0CTL0)
0/1 0 0 0 0
TQ0CTL0
Select count clock
0: Stop counting
1: Enable counting
0/1 0/1 0/1
TQ0CKS2 TQ0CKS1 TQ0CKS0TQ0CE